library ieee;
use ieee.std_logic_1164.all;
package custom_types is
  type bus16x32 is array(15 downto 0) of std_logic_vector(31 downto 0);
  type in_pipeline_stage is record
    A 	: std_logic_vector(31 downto 0);
    B 	: std_logic_vector(31 downto 0);
    Op  : std_logic_vector(3 downto 0);
  end record in_pipeline_stage;
end package custom_types;
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